1. Technical Field of the Invention
The present invention relates to power supplies for integrated circuit memories and, more particularly, to a programmable source bias scheme for supplying an offset power supply set of voltages for use in an SRAM standby mode operation.
2. Description of Related Art
Reference is made to FIG. 1 which is a schematic diagram of a standard six transistor static random access memory (SRAM) cell 10. The cell 10 includes two cross-coupled CMOS inverters 12 and 14, each inverter including a series connected p-channel and n-channel transistor pair. The inputs and outputs of the inverters 12 and 14 are coupled to form a latch circuit having a true node 16 and a complement node 18. The cell 10 further includes two transfer (pass gate) transistors 20 and 22 whose gate terminals are controlled by a word line (WL). Transistor 20 is connected between the true node 16 and a true bit line (BLT). Transistor 22 is connected between the complement node 18 and a complement bit line (BLC). The source terminals of the p-channel transistors in each inverter 12 and 14 are coupled to receive a high voltage VH at a high voltage VH node, while the source terminals of the n-channel transistors in each inverter 12 and 14 are coupled to receive a low voltage VL at a low voltage VL node. The high voltage VH and the low voltage VL comprise a power supply set of voltages for the cell 10. Conventionally, the high voltage VH is a positive voltage (for example, 1.5V) and the low voltage VL is a ground voltage (for example, 0V). In an integrated circuit including the SRAM cell 10, this power supply set of voltages may be received at pins of the integrated circuit, or may instead be generated on chip by a voltage converter circuit which receives some other set of voltages received from the pins of the chip. The power supply set of voltages VH and VL are conventionally applied to the SRAM cell 10 at all times that the cell/integrated circuit is operational.
Reference is now made to FIG. 2 which is a block diagram of a static random access memory (SRAM) array 30. The array 30 includes a plurality of SRAM cells 10 arranged in a matrix format. The number of cells 10 included in the array 30 can widely vary depending on the circuit designer's needs. The high voltage VH and the low voltage VL of the power supply set of voltages is applied to the array 30 and distributed over the array in a manner well known to those skilled in the art to the individual ones of the included cells 10 (for application to the source terminals of the p-channel and n-channel transistors as shown in FIG. 1).
Reference is now made to FIG. 3 which is a block diagram of a static random access memory (SRAM) array 40. The array 40 is comprised of a plurality of memory blocks 42 arranged in a matrix format. The number of blocks 42 included in the array 40 can widely vary depending on the circuit designer's needs. Each block 42 includes a plurality of SRAM cells 10 also arranged in a matrix format. The number of cells 10 included in the block 42 can widely vary depending on the circuit designer's needs. The high voltage VH and the low voltage VL Of the power supply set of voltages is applied to the array 40 and distributed over the array by a power distribution grid in a manner well known to those skilled in the art to each of the blocks 42. Power is then passed on to the individual ones of the included cells 10 within each block 42 (for application to the source terminals of the p-channel and n-channel transistors as shown in FIG. 1).